1. Field of the Invention
The present invention relates to a semiconductor memory device and particularly to a read only memory used for digital signal processing applications.
2. Description of the Background Art
As one type of semiconductor memory devices, there have been read only memories (referred to as "ROMs" hereinafter) for storing information such as predetermined programs or data, and these ROM's have been widely used for various purposes.
In digital signal processing fields, these ROM's are used as hold means for coefficients and storage means for operations of a table look-up type. In the operations of the table look-up type, results of the operations corresponding to inputs are prestored in a form of a table, and a result corresponding to an applied input is searched in the table for outputting. In the ROM's storing such tables, the inputs are used as addresses, and the results of operations are stored correspondingly to the respective addresses.
In integrated circuit devices directed to a digital signal processing, the ROM's are assembled in these integrated circuit devices. A major reason for which the ROM is used for such signal processing application is that one memory cell is formed of one transistor and thus a required hardware is smaller in size or scale than other memory devices such as SRAM's (static random access memories), upon storage of data of a common capacity. Thus, the ROM's have been used for the above purposes because of low costs and relatively small occupied area.
FIG. 1 schematically illustrates general structures of a ROM. In FIG. 1, the ROM includes a memory cell array 6 in which memory cells for storing information are disposed in a matrix of rows and columns, an address buffer 7 and an address decoder 8, both of which serve to select a desired memory cell in the memory cell array 6.
The address buffer 7 receives an externally applied address input to generate an internal address corresponding to the received address input. The address decoder 8 decodes the internal address received from the address buffer 7 to select the corresponding memory cell in the memory cell array 6.
The address input may include both of row and column addresses which designate the row and column in the memory cell array 6, respectively, or may include only the row address. The column address is not required if the ROM has a structure in which data in memory cells in one row are simultaneously read out, for instance, in a structure in which one row in the memory cell array 6 provides one word. In this case, the address input includes only the row address. If the ROM has such a structure that one row is one page and includes a plurality of words, it is necessary to read out the data in desired memory cells among the memory cells in one row. In this case, both of the row address and the column address are required for respectively designating the row and column addresses of the memory cells. In this case, the address input includes both the column and row addresses.
Thus, the address decoder 8 has a structure dependent on the structure of the ROM, and specifically, may include only the row decoder for selecting a row in the memory cell array 6 or both of the row and column decoders respectively selecting a row and a column in the memory cell array 6. In FIG. 1 illustrating the ROM, the address decoder 8 is generally illustrated to include both of the cases described above.
The ROM shown in FIG. 1 further includes a control signal generator circuit 10 responsive to externally applied control signals CE and OE for generating internal control signals such as signals AT, AT', .phi.p and OE, an output circuit 9 which is activated in response to the internal control signal OE, to sense and amplify the data in the memory cells selected by the address decoder 8 for sending to an external as an output data D, and a precharge circuit 41 for precharging bit lines (which are internal data transmission line; and will be described later) in the memory cell array 6, for instance, in a standby state of the ROM to a predetermined reference potential such as a supply potential Vcc level.
The internal control signal AT provides a timing at which an address input 7 is strobed to generate an internal address in the address buffer. The internal control signal AT' provides a timing for address decoding in the address decoder 8. The output circuit 9 generally includes a sense amplifier for amplifying data of a selected memory cell in the memory cell array 6 and an output buffer for performing a buffer processing on this amplified output to generate an output data. The internal control signal OE determines a timing for activating this output circuit 9. The output buffer may be in an output high impedance state when the control signal OE is inactivated, or may be constructed to have an output fixed at a predetermined reference potential. The sense amplifier is activated to execute the amplifying operation in response to this internal control signal OE.
The precharge circuit 41 is activated in response to the internal control signal .phi.p to precharge respective bit lines to the predetermined reference potential.
The externally applied control signal CE is a control signal for enabling the ROM. The control signal OE is a control signal for providing a data output timing for the ROM. The precharge signal .phi.p is generally in an activated state when the control signal CE is in an inactivated state.
FIG. 2 schematically illustrates a structure of a memory cell contained in the memory cell array 6 in the ROM shown in FIG. 1. In FIG. 2, ROM memory cell MC includes one MOS transistor (insulated gate type field effect transistor) 1. This MOS transistor 1 has a gate connected to a word line 2 and a source connected to a reference potential line 4 which supplies a first reference potential Vss (e.g., a ground potential). A drain of the MOS transistor 1 is selectively connected to or disconnected from a bit line 3, depending on a stored data in this memory cell MC. Although the source and drain of the MOS transistor 1 are determined in accordance with its application, a conduction terminal connected to the bit line will be called as the drain in the following description. Connection and disconnection of a region 16 encircled by a broken line in FIG. 2 is determined depending on whether a wiring is masked or not in fabrication steps of the transistor. The bit line 3 is provided at its one end with a precharge transistor 15 which is responsive to the precharge signal .phi.p for connecting the bit line 3 to a second reference potential Vcc which is, for instance, an operation power supply potential. Now, an operation of the ROM shown in FIGS. 1 and 2 will be described with reference to an operation waveform diagram in FIG. 3.
If the control signal CE is at "H" and the ROM is in the disabled state (unselected state) and thus in the standby state, the precharge signal .phi.p is at the "H" level. A precharge transistor 15 is in the ON-state, and the bit line 3 is precharged to "H", i.e., the supply potential Vcc level.
When the control signal CE falls to "L", this ROM is enabled to start a memory cycle. In response to the fall of this control signal CE, the address buffer 7 strobes an externally applied address input and generates an internal address. This internal address is generated at the timing determined by the control signal AT. The address decoder 8 decodes the internal address from the address buffer 7, and selects a corresponding row in the memory cell array 6 to transmit a row selection signal WL to the word line corresponding to the selected row. The decoding timing in the address decoder 8 is determined by the internal control signal AT'. When the row selection signal WL is transmitted to the selected word line to increase the potential thereof to "H", the transistor 1 in the memory cell MC connected to this selected word line is turned on.
Description will further be made with reference to such a case that the drain of the transistor 1 is connected to the bit line 3 through the region 16. The precharge transistor 15 connected to the bit line 3 is turned off when the memory cycle starts, and the bit line 3 is held at a floating state of "H". In this case, a precharged charges in the bit line 3 are discharged through the turned-on transistor 1 to a first reference potential Vss, resulting in lowering of the potential of the bit line 3.
If a wiring is not formed in the region 16 between the transistor 1 and the bit line 3, there is no discharging path for the charges between the transistor 1 and the bit line 3. In this condition, the bit line 3 maintains its precharged potential. The potential of this bit line 3 will be sensed and amplified by an amplifier included in the output circuit 9. An activation of this amplifier is effected by the control signal OE. This may also be executed by a delay signal of the control signal CE.
When the control signal OE falls to "L", the output circuit 9 (output buffer) is activated, and the data in the selected memory cell is output as the output data D after amplification. FIG. 3 illustrates a case in which the signal OE is at "H" and the output data D is in a high impedance state. When the output control signal OE falls to "L", the output data D is initially invalid and will be valid after a predetermined time. This is due to a fact that it is unclear whether a value of the output data at the time of falling of this control signal OE is the data in the selected memory cell. This is due to a fact that the activating timing of the amplifier included in the output circuit 9 is determined by the control signal OE or CE, and, when the output circuit 9 is activated, it is unclear whether the data in the selected memory cell is output or not as the output data D through the output buffer after amplification by the amplifier.
In the operation waveform diagram shown in FIG. 3, there is illustrated an example, in which holding of the data "1" by the memory cell MC corresponds to a case in which the region 16 shown in FIG. 2 is disconnected and the bit line 3 holds the precharged potential, and in which holding of the data "0" by the memory cell MC corresponds to a case in which the region 16 is connected and the potential of the bit line 3 lowers.
When one memory cycle is completed, the control signal CE rises to "H". The control signal CE can return to "L" only after elapsing of a precharging time Tb. This time Tb is a time required for precharging the bit line 3 to the operation power supply potential Vcc level.
As described above, since the ROM's have simple memory cell structures suitable for high degree of integration, they are generally and widely used for storing data and programs which require no change. However, in the ROM's, one memory cell is formed of one transistor, so that the number of the required memory transistors corresponds to the memory capacity. FIG. 4 illustrates a structure of the ROM of 8 words.times.1 bit.
In FIG. 4, eight word lines 2e, 2f, 2g, 2h, 2i, 2j, 2k and 2l and one bit line 3 form intersections at which memory cell transistors 1e, 1f, 1g, 1h, 1i, 1j, 1k and 1l are disposed, respectively.
The memory transistors 1e, 1g, 1i and 1j are connected at their drains through the regions 16 to the bit line 3. The drains of the memory transistors 1f, 1h, 1k and 1l are isolated at the wiring regions 16 from the bit line 3. Sources of the respective memory transistors 1e-1l are connected to a ground line 4, which supplies the ground potential, i.e., the first reference potential (referred to hereinafter as "ground potential"), and gates thereof are connected to the corresponding word lines 2e-2l, respectively.
The address input for designating the memory cell transistors is externally applied and is decoded by the address decoder 8 (see FIG. 1) to designate a word line to which the row selection signal WL is transmitted. In the structure shown in FIG. 4, the row selection signal WL is transmitted to one of the word lines 2e-2l. It is assumed that the word lines 2e-2l correspond to address 1-address 8, respectively.
In the ROM of 8 words.times.1 bit, the address inputs, potentials in the word lines, selected memory cell transistors (turned-on transistors) and the data read at respective times have a relationship listed in FIG. 5.
For example, if the address input is the address 1, the word line 2e is selected and the potential thereof rises to "H" so that the memory cell transistor 1e is turned on. Since this memory cell transistor 1e has the drain connected to the bit line 3, the potential of the bit line 3 falls to "L" and "0" is read as the data. Similarly, in the other memory cell transistors, the potential of the word line corresponding to an address input rises to "H" and the memory cell transistor connected to the selected word lines is turned on, respectively, so that the data to be read is determined in accordance with the connection conditions between the drain and the bit line 3.
As described above, the memory cell of the ROM of 8 words.times.1 bit requires one transistor per each memory cell and thus totally requires eight transistors. Generally, the ROM of N words.times.M bits requires N.times.M transistors in the memory cell array. Therefore, an increase of the capacity of the ROM causes a problem that the number of the memory cell transistors included therein increases and thus the occupied area thereof also increases. Further, if the memory cell array area is restricted, it is difficult to obtain the memory cell transistor formation region having a sufficient area, and thus the memory cell transistors having high reliability cannot be obtained.
If ROM's described above are used for a digital signal processing purpose, a so-called bank system in which the ROM's are switched in accordance with process contents is often employed. FIG. 6 schematically illustrates the structure of ROMs for achieving an operation in a table look-up manner.
In FIG. 6, there are illustrated a first ROM 31a and a second ROM 31b which have stored sets of coefficients corresponding to operation modes, respectively. Either of the first and second ROM's 31a and 31b is selected in accordance with the operation mode, i.e., in accordance with the processing contents by an operation mode designating signal SA which is selectively applied to the selection inputs SE of the first and second ROM's 31a and 31b.
The ROM 31a has stored output results a.multidot.x corresponding to inputs x and the ROM 31b has stored output results b.multidot.x corresponding to the inputs x. These inputs x are applied to the ROM's 31a and 31b as the address inputs, respectively.
In the ROM bank structure described above, if the operation designating signal SA has selected the ROM 31a, outputs z=a.multidot.x are obtained from the inputs x. If the operation mode designating signal SA has selected the ROM 31b, outputs z=b.multidot.x are obtained from the inputs x. As an example of the bank structure, such a case can be envisaged that one of the ROM's outputs results of multiplication of the inputs x by 2 and the other ROM outputs results of division of the inputs x by 2.
The bank structure in which the banks are switched in accordance with the operation modes require a plurality of ROM's, so that, assembling of the ROM's in an integrated circuit device dedicated to the digital signal processing causes a problem of a large occupied area. In this case, although combinations of the inputs x and the operation mode designating signals SA may be used as the addresses so as to provide two banks only by one ROM, this one ROM requires the memory capacity same as those of the two ROM's shown in FIG. 6, resulting in large scales or sizes.
An image processing purpose is a typical example of the digital signal processing purposes. In the image processing field, transform such as orthogonal transform or conversion of sampling frequencies is often performed. For example, in discrete Fourier transform, coefficients for respectively executing Fourier transform and inverse Fourier transform as well as matrix substitution for a butterfly operation are stored in different ROM's.
FIG. 7 schematically illustrates structures for a matrix operation circuit in a semiconductor integrated circuit device dedicated to such an image processing. Structure of the integrated circuit device for the signal processing shown in FIG. 7 is disclosed, for instance, in "Nikkei Electronics", No. 492, Feb. 5, 1990, pp 174-175. FIG. 7 illustrates a part of the circuit structure for performing a two-dimensional discrete cosine transform, and the illustrated device includes a matrix operation circuit 33 as well as ROM's 32a, 32b, 32c and 32d for storing sets of predetermined coefficients, respectively. In order to set one of these ROM's 32a-32d in a selected state, an externally applied operation mode designating signal SB (2 bits) is selectively applied to selection inputs SE of the ROM's 32a-32d.
A matrix operation circuit 33 performs a transform operation using pixels of predetermined n rows by m columns (e.g., 8 rows by 8 columns) as one unit. That is; when one unit block of pixels Xij is applied, the matrix operation circuit 33 multiplies this applied input Xij by the coefficient from one of the ROM's 32a-32d and the multiplied result will be sequentially accumulated to form an output .SIGMA.Aij.multidot.Xij, where Aij is a coefficient supplied from the selected ROM.
In the structures shown in FIG. 7, one of the coefficient ROM's is selected in accordance with the operation mode, so that the predetermined operation is performed in the matrix operation circuit 33 with respect to the input Xij and the coefficient from this selected ROM. In this operation, if resolution (constituent bit number, i.e., data width) of the input Xij is increased and the scales of the unit block handled by the matrix operation circuit 33 are increased, the number of the coefficients stored in the respective ROM's 32a-32d is increased and the data width of the coefficients is also increased, resulting in increase of capacities of the ROM's. Therefore, in the structures operable to switch these ROM's in accordance with the respective operation modes, a plurality of ROM's are required and the scales of the ROM part for storing the coefficients are increased, which impedes a high integration.
The structure shown in FIG. 7 employs the four coefficient ROM's for a reason that it supports following ROM's, i.e., a ROM storing coefficients for the discrete cosine transform, a ROM storing coefficients for performing an inverse discrete cosine transform, a ROM storing coefficients by which a matrix substitution is executed for a butterfly operation, and a ROM for storing coefficients utilized to obtain a function as a filter (low-pass filter) in a loop for reducing a block distortion generated in a decoding operation with the discrete cosine transform. When the function as the filter in the loop is utilized, the matrix operation circuit 33 functions as one digital filter.
Further, as shown in FIG. 8, a ROM is often used as a program ROM for storing a predetermined program. This program ROM 35 usually stores a microcoded program, and has such an advantage that a CPU (central processing unit) 36 can execute a predetermined processing program at a high speed without accessing an external storage device. For the control purposes and others, if the above CPU 36 and program ROM 35 are used as a control circuit, they are often used in a one-chip microcomputer. If the scales of the processing program stored in this program ROM 35 are increased, the scales of the program ROM 35 are also increased, and thus such control circuit can not be constructed to be compact in one chip.
Then, description will be made with respect to a control system which determines the system to be normal only when both of a state variable at a point A and a state variable at a point B satisfy predetermined conditions. The input x indicates a given state variable at the point A and the input y indicates a given state variable at the point B. Consideration will be made with respect to the control system adapted to hold values ax and ay, which are the inputs x and y multiplied by a coefficient a, at predetermined reference values p and q, respectively. A structural example of the above control system is illustrated in FIG. 9.
In FIG. 9, this control system includes a first ROM 41 storing multiplied results ax of the inputs x in a form of a table, a second ROM 42 for storing multiplied results ay of the inputs y in a form of a table, a subtracter 43 which subtracts the predetermined reference value p from an output ax of the first ROM 41, a subtracter 44 which subtracts the second reference value q from an output ay of the second ROM 42, and an operation circuit 45 adapted to determine that the system is in a normal operation and generate a normal indication signal only when both of the outputs of the subtracter 43 and 44 are smaller than a predetermined value. As an example of a system, there may be a case in which the inputs x and y are detected outputs of thermo-couples, and the coefficient "a" is determined to convert these detected outputs to temperatures.
The operation circuit 45 is adapted to output the system normal indication signal only when the output ax-p from the subtracter 43 is not more than a first predetermined value (allowable error) and the output ay-q from the subtracter 44 is not more than a second predetermined value. In this case, the inputs x and y are required to be processed simultaneously, so that two ROM's, i.e., the first ROM 41 and the second ROM 42 storing the same coefficient are required. In this case, although the first and second ROM's 41 and 42 have same storage contents, the separate and different inputs x and y cannot be applied simultaneously to one of the ROM's. Therefore, such a problem is caused that the control system described above cannot have compact structures and a small occupied area.